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FEATURES 24 dB Gain 4 dB Noise Figure Easy Match to SAW Filters Output Limiter Adjustable +8.5 dBm to +12 dBm 700 MHz Bandwidth 10 V Single or Dual 5 V Power Supply 300 mW Power Dissipation APPLICATIONS ADC IF Drive Amp Communications Receivers PCS/Cellular Base Stations GSM, CDMA, TDMA
Differential, Low Noise IF Gain Block with Output Clamping AD6630
FUNCTIONAL BLOCK DIAGRAM
NC 1 NC 2 IP2 3 IP1 4 IP1 5 IP2 6 CLLO 7 CLHI 8 NC = NO CONNECT + + +
AD6630
16 15 14 13 12 11 10 9
VCC CD1 OP VEE CMD OP CD2 VCC
PRODUCT DESCRIPTION
The AD6630 is an IF gain block designed to interface between SAW filters and differential input analog-to-digital converters. The AD6630 has a fixed gain of 24 dB and has been optimized for use with the AD6600 and AD6620 in digitizing narrowband IF carriers in the 70 MHz to 250 MHz range. Taking advantage of the differential nature of SAW filters, the AD6630 has been designed as a differential in/differential out gain block. This architecture allows 100 dB of adjacent channel blocking using low cost SAW filters. The AD6630 provides output limiting for ADC and SAW protection with 10 phase variation in recovery from overdrive situations. Designed for "narrow-band" cellular/PCS receivers, the high linearity and low noise performance of the AD6630 allows for implementation in a wide range of applications ranging from
GSM to CDMA to AMPS. The clamping circuitry also maintains the phase integrity of an overdriven signal. This allows phase demodulation of single carrier signals with an overrange signal. While the AD6630 is optimized for use with the AD6600 Dual Channel, Gain Ranging ADC with RSSI, it can also be used in many other IF applications. The AD6630 is designed with an input impedance of 200 and an output of 400 . In the typical application shown below, these values match the real portion of a typical SAW filter. Other devices can be matched using standard matching network techniques. The AD6630 is built using Analog Devices' high speed complementary bipolar process. Units are available in a 300 mil SOIC (16 leads) plastic surface mount package and specified to operate over the industrial temperature range (-40C to +85C).
AD6630
MAIN LOCAL OSCILLATOR AD6600 AD6620 DSP
AD6630
DIVERSITY
Figure 1. Reference Design
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
AD6630-SPECIFICATIONS
NORMAL OPERATING CONDITIONS
Parameter (Conditions) SINGLE SUPPLY VOLTAGE POSITIVE SUPPLY VOLTAGE NEGATIVE SUPPLY VOLTAGE AMBIENT TEMPERATURE PACKAGE THERMAL RESISTANCE OPERATING FREQUENCY1 70 Min 8.5 4.25 -5.25 -40 80 250 5.0 -5.0 Typ Max 10.5 5.25 -4.25 +85 Units V V V C C/W MHz
DC SPECIFICATIONS Inputs should be AC coupled.)
Parameter SUPPLY CURRENT OUTPUT DC LEVEL Temp Full Full
(TMIN = -40 C, TMAX = +85 C. Output dc levels are nominally at VM, where VM = VCC + VEE = [+5 V + (-5 V)] = 0.
Test Level II II VM-150
Min
Typ 30
Max 48 VM+150
Units mA mV
AC SPECIFICATIONS performance limits are correlated to 5 MHz testing based on characterization data.)
Parameter1 GAIN (POWER) @ 70 MHz GAIN (POWER) @ 250 MHz -3 dB BANDWIDTH OUTPUT REFERRED IP3 @ 70 MHz
2 2
(TMIN = -40 C, TMAX = +85 C. All AC production tests are performed at 5 MHz. 70 MHz and 250 MHz
Test Level II II V V V V V II II II II V V V V V V IV IV IV 8.5 7.5 11 9 3700 200 2 400 2 4 11 13.8 9.25 12.5 14.3 10.6
Temp Full Full +25C Full Full Full Full Full Full Full Full +25C +25C +25C +25C +25C +25C Full Full Full
4, 5 3, 5
Min 23 22
Typ 24 23 700 22 19 45 45
Max 25 24
Units dB dB MHz dBm dBm dBm dBm dBm dBm dBm dBm V/s pF pF dB dBm dBm dBm
OUTPUT REFERRED IP3 @ 250 MHz OUTPUT REFERRED IP2 @ 70 MHz2
OUTPUT REFERRED IP2 @ 250 MHz2 OUTPUT REFERRED 1 dB COMPRESSION POINT @ 70 MHz LOW LEVEL CLAMP3 OUTPUT REFERRED 1 dB COMPRESSION POINT @ 250 MHz LOW LEVEL CLAMP3 OUTPUT REFERRED 1 dB COMPRESSION POINT @ 70 MHz HIGH LEVEL CLAMP4 OUTPUT REFERRED 1 dB COMPRESSION POINT @ 250 MHz HIGH LEVEL CLAMP4 OUTPUT SLEW RATE INPUT IMPEDANCE (REAL) INPUT CAPACITANCE OUTPUT IMPEDANCE (REAL) OUTPUT CAPACITANCE NOISE FIGURE LOW LEVEL CLAMP MAXIMUM OUTPUT @ 70 MHz3, 5 HIGH LEVEL CLAMP MAXIMUM OUTPUT @ 70 MHz
LOW LEVEL CLAMP MAXIMUM OUTPUT @ 250 MHz
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Parameter HIGH LEVEL CLAMP MAXIMUM OUTPUT @ 250 MHz PHASE VARIATION CMRR PSRR
8 7 6 4, 5
Temp Full +25C +25C +25C
Test Level IV V V V
Min
Typ 11.2 9 50 30
Max 12.2
Units dBm Degree dB dB
NOTES 1 All specifications are valid across the operating frequency range when the source and load impedance are a conjugate match to the amplifier's input and output impedance. 2 Test is for two tones separated by 1 MHz for IFs at 70 MHz and 250 MHz at -23 dBm per tone input. 3 Low Level Clamp is selected by connecting pin CLLO to the negative supply, while pin CLHI is left floating. Clamping can be set at lower levels by connecting pin CLLO and CLHI to the negative supply through an external resistor. 4 High Level Clamp is selected by connecting pin CLHI to the negative supply, while pin CLLO is left floating, this allows the maximum linear range of the device to be utilized. 5 Output clamp levels are measured for hard clamping with a +3 dBm input level. Valid for a maximum input level of +8 dBm/200 = 3.2 V p-p--differential. 6 Measured as the change in output phase when the input level is changed from -53 dBm to +8 dBm (i.e., from linear operation to clamping). 7 Ratio of the differential output signal (referenced to the input) to the common-mode input signal presented to all input pins. 8 Ratio of signal on supply to differential output (<500 kHz). Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
EXPLANATION OF TEST LEVELS
Parameter Single Supply Voltage Positive Supply Voltage Negative Supply Voltage Input Power Storage Temperature Junction Temperature ESD Protection
Min -0.5 -0.5 -5.75 -65 1
Max 11.5 5.75 0.5 +8 +150 +150
Units V V V dBm C C kV
I.
100% production tested.
II. 100% production tested at +25C, and guaranteed by design and analysis at temperature extremes. III. Sample tested only. IV. Parameter guaranteed by design and analysis. V. Parameter is typical value only. VI. 100% production tested at +25C, and sample tested at temperature extremes.
ORDERING GUIDE
Model AD6630AR AD6630AR-REEL AD6630R/PCB
Temperature Range -40C to +85C (Ambient) -40C to +85C (Ambient)
Package Description 16-Lead Wide Body SOIC AD6630AR on 1000 PC Reel Evaluation Board with AD6630AR
Package Option R-16
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6630 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD6630
PIN FUNCTION DESCRIPTION PIN CONFIGURATION
Pin No 1, 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin Name NC IP2 IP1 IP1 IP2 CLLO CLHI VCC CD2 OP CMD VEE OP CD1 VCC
Description No Connect Input Input Input Input Clamp Level Low Pin Clamp Level High Pin +VCC Supply Clamp Decoupling Output DC Feedback Decoupling -VEE Supply Output Clamp Decoupling +VCC Supply
NC 1 NC 2 IP2 3 IP1 4
16 15 14
VCC CD1 OP
VEE TOP VIEW IP1 5 (Not to Scale) 12 CMD
13
AD6630
IP2 6 CLLO 7 CLHI 8
11 10 9
OP CD2 VCC
NC = NO CONNECT
Typical Performance Characteristics
24 23 INTERCEPT POINT - dBm 22 21 20 19 18 17 16 70 8 70 1dB COMPRESSION POINT 12 HIGH CLAMP 13
11
10 LOW CLAMP 9
100 INPUT FREQUENCY - MHz
300
100 INPUT FREQUENCY - MHz
300
Figure 2. 3rd Order Intercept (IP3) vs. Frequency
Figure 4. 1 dB Compression Point (Typical)
25
14
-40 C 24 GAIN - dB +25 C +85 C 23
OUTPUT AMPLITUDE - dBm
13 HIGH CLAMP 12
11 LOW CLAMP 10
22 70 100 INPUT FREQUENCY - MHz 300
9 70 100 INPUT FREQUENCY - MHz 300
Figure 3. Gain vs. Frequency
Figure 5. Clamp Level vs. Frequency
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-1dB 15dB -9dB -2dB 15dB -5dB 24dB -5dB
-2
8d
Bm Bm 9d 4d -2 -1 LOCAL OSCILLATOR Bm
-2
3d
Bm dBm dBm dBm dBm 9 5 0 5 -1 -1 -2
Bm 4d
MAIN
AD6630
SAW SAW
AD6600
AD6620
DSP
DIVERSITY
ANTENNA -104dBm -43dBm -28dBm -16dBm -15dBm
AD6630 INPUT -91dBm -30dBm -15dBm -3dBm -2dBm
AD6630 OUTPUT -67dBm -6dBm +9dBm +9dBm +9dBm
AD6600 INPUT -71dBm -10dBm +4dBm +4dBm +4dBm
Figure 6. GSM Design Example
THEORY OF OPERATION
The AD6630 amplifier consists of two stages of gain. The first stage is differential. This differential amplifier provides good common-mode rejection to common-mode signals passed by the SAW filter. The second stage consists of matched current feedback amplifiers on each side of the differential pair. These amplifiers provide additional gain as well as output drive capability. Gain set resistors for these stages are internal to the device and cannot be changed, allowing fixed compensation for optimum performance. Clamping levels for the device are normally set by tying CLLO or CLHI pins to the negative supply. This internally sets bias points that generate symmetric clamping levels. Clamping is achieved primarily in the output amplifiers. Additional input stage clamping is provided for additional protection. Clamping levels may be adjusted to lower levels as discussed below.
APPLICATIONS
This equation is derived from measured data at 170 MHz. Clamp levels vary with frequency, see Figure 5. Output clamp levels less than 8.5 dBm will result in damage to the clamp circuitry unless the absolute maximum input power is derated. Similarly, the output clamp level cannot be set higher than 12 dBm.
VEE R CLAMP GENERATOR
Figure 7. Clamp Level Resistor
Matching SAW Filters
The AD6630 is designed to easily match to SAW filters. SAW filters are largely capacitive in nature. Normally a conjugate match to the load is desired for maximum power transfer. Another way to treat the problem is to make the SAW filter look purely resistive. If the SAW filter load looks resistive there is no lead or lag in the current vs. voltage. This may not preserve maximum power transfer, but maximum voltage swing will exist. All that is required to make the SAW filter input or output look real is a single inductor shunted across the input. When the correct value is used, the impedance of the SAW filter becomes real.
The AD6630 provides several useful features to meet the needs of radio designers. The gain and low noise figure of the device make it perfect for providing interstage gain between differential SAW filters and/or analog-to-digital converters (ADC). Additionally, the on-board clamping circuitry provides protection for sensitive SAW filters or ADCs. The fast recovery of the clamp circuit permits demodulation of constant envelope modulated IF signals by preserving the phase response during clamping. The following topics provide recommendations for using the AD6630 in narrowband, single carrier applications.
Adjusting Output Clamp Levels
9.7 400 3pF 47nH 15.2pF
Normally, the output clamp level is set by tying either CLLO or CLHI to ground or VEE . It is possible to set the limit between 8.5 dBm and 12 dBm levels by selecting the appropriate external resistor. To set to a different level, CLLO and CLHI should be tied together and then through a resistor to ground. The value of the resistor can be selected using the following equation. R= 14.4 - OUTPUTCLAMP (dBm) 0.0014
Figure 8. Saw Filter Model (170 MHz)
EVALUATION BOARD
Figures 9, 10 and 12 refer to the schematic and layout of the AD6630AR as used on Analog Devices' GSM Diversity Receiver Reference Design (only the IF section is shown). Figure 14 references the schematic of the stand-alone AD6630 evaluation board and uses a similar layout. The evaluation board uses center tapped transformers to convert the input to a differential signal and AD6630 outputs to a single connector to simplify evaluation. C8, C9 and L2 are optional reactive components to tune the load for a particular IF frequency if desired. -5-
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AD6630
+10V
U100A
NC1 SMA CHNA C1 L1A C2 12 VI GND 1 2 3 4 7 8 9 10 L1 NC2 11 VI VO 5 C100 0.1 F L2 VO 6 C101 0.1 F IP2 IP1 IP1B IP2B CL1 CL2 VCC1 CD1 OP VEE CMD OPB CD2 VCC2 12 C104 0.1 F C103 0.1 F C102 0.1 F VI GND 1 2 3 4 7 8 9 10 VO 11 L4 VI VO 5 L6 6 TO AD6600
SAW1
SAW2
AD6630
Figure 9. Reference Design Schematic (One Channel)
Figure 10. Reference Design PCB Layout
Figure 12. Reference Design Component Placement (Two Channels Shown)
OUTPUT AMP + + - + DIFF AMP - VCC
OUTPUT AMP -
IP1 TO OUTPUT AMPLIFIER
200
200 IP1 BIAS TO OUTPUT AMPLIFIER IP2
200 IP2 CLP CLAMP GENERATOR CLN
200
CLHI CLLO
VEE
Figure 11. Functional Block Diagram
Figure 13. Equivalent Input Circuit
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J1 PCTB3 3 21 C13 1F 1 2 +- 2 AGND J6 SMA 2 1 C17 10nF R3 R1 200 TP1 AGND 1 TEST P C16 10nF
C18 1F AGND - C21 10nF + 11
AGND J3
AGND
AD6630
1 AGND J7 SMA 2 1 6 T1 1 2 4 AGND 3 C1 10nF L1 470nH C12 10nF C11 10nF 2 3 4 5 6 7 8 J2 C20 1nF
U1
NC1 NC2 IP2 IP1 IP1B IP2B CL1 CL2 VCC1 CD1 OP VEE CMD OPB CD2 VCC2
16 15 14 13 12 11 10 9
C15 1nF C5 10nF
C10 100nF
C2 10nF T2 3 4 2 1 6 AGND 1 2 J8 SMA
C6
10nF
C8
C9
L2
TC4-1W AT224 AGND
C7
10nF C3 10nF
TC 8-1 AT224 1 TP2 TEST P
C14 1nF C19 100nF AGND
C4 100nF AGND R2 200 AGND
Figure 14. Evaluation Board Schematic
Table I. Typical S Parameters
Frequency (MHz) 70 170 200 250
S11 224.5 -4.52 264.8 -32.9 227.9 -34.8 209.5 -36.2
S12 -41.0 -3.0 -31.4 0 -41.0 -5 -40.6 -2.3
S21 24.1 -8.8 23.5 -22.5 23.2 -26.4 22.9 -38.9
S22 394.3 -8.6 382.4 -21.9 353.0 -25.4 328.9 -29.2
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AD6630
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Wide Body SOIC (R-16)
C3412-8-10/98
0.0291 (0.74) x 45 0.0098 (0.25) 0.0500 (1.27) 0.0157 (0.40) 0.4133 (10.50) 0.3977 (10.00)
16 9
1
8
PIN 1 0.0118 (0.30) 0.0040 (0.10)
0.1043 (2.65) 0.0926 (2.35)
0.0500 (1.27) BSC
0.0192 (0.49) SEATING 0.0138 (0.35) PLANE
0.4193 (10.65) 0.3937 (10.00) 8 0.0125 (0.32) 0 0.0091 (0.23)
0.2992 (7.60) 0.2914 (7.40)
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PRINTED IN U.S.A.

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